Areas of Expertise

System on Chip(SOC), Network on Chip(NOC), Low Power Design, Power Management, Computer Architecture

Work Experience

• Developing hybrid hardware software co emulation platform for future SoC products.

Fall 2006 – May 2011

Research Assistant at Texas A&M University (College Station, TX)

·    Designed a low power router buffer using nanoscale CMOS SRAM and adaptive storage encoding.

·    Designed a flow aware dynamic buffer management with novel flow control for NoC routers.

·    Designed ant system based intelligent power sharing algorithm for NoC based Multicore SoC.

·    Developed a NoC based full system SoC simulation platform using SystemC.

·    Developed a smart battery that can manage an array of cells and optimize discharge for higher lifetime.

·    Designed a fast low power hardware scheduler based on the Pfair scheduling algorithm for optimal multiprocessor scheduling.    

May 2010 – Dec 2010

Development Engineer (Co-Op) at IBM Systems and Technology Group (Austin, TX)

·    Developed Simics simulation models for validation of power management subsystem in future Power^TM processor

·    Validated design VHDL against architectural specification by designing component test cases.

·    Designed complex voltage and frequency controller for DVFS in high end Power^TM system.

·    Developed Python translation tool to automatically parse specification into validation model code.

Skills

Software

C, C++, C#, JAVA, BASIC, Perl, Python, RISC/x86 Assembly, UNIX Shell Scripting

Hardware

SystemC , Verilog, VHDL, System Verilog

EDA Tools

Xilinx ISE, Synopsis VCS, Design Compiler, Tetramax, Simics

Education

2006 - Present

PhD in Computer Engineering, Texas A&M University, Exp. Graduation in August 2011.

2002 - 2006

B. Tech (Honors) in Computer Science & Engineering, IIT Kharagpur, India, 2006.

Awards and Achievements

ThinkSwiss Research Fellowship, 2007; 26^th Rank in IIT JEE, India 2002; National Scholarship, India, 2000

Publications

[1]  S. K. Mandal, R. Denton, S. P. Mohanty and R. Mahapatra, "Low Power Nanoscale Buffer Management for Network on Chip Routers", In Proceedings of GLSVLSI 2010.

[2]  J Lee, S. K. Mandal and R. Mahapatra, "Application-Aware Online Testing for Many-Core SoC", In Proceedings of Asian Test Symposium, 2010.

[3]  S. K. Mandal, R. Mahapatra, “PowerAntz: Ant behavior inspired power budget distribution scheme for Network on Chip systems”, Microelectronics Journal, August 2010. Vol. 41. Issue 8, pp. 523-531.

[4]  A. Mandal, S. K. Mandal, A. Tripathy, and R. Mahapatra, "A Bio-inspired Framework for Secure System on Chip," In Proceedings of Workshop on SoC Architecture, Accelerators and Workload, Jan 2010.

[5]  N. Gupta,  S. K. Mandal, A. Mandal, J. Malave & R. N. Mahapatra, "A Hardware Scheduler for Real Time Multiprocessor System on Chip", 23rd International Conference on VLSI Design, 2010, pp.264-269.

[6]  S. K. Mandal, P. Bhojwani, S. P. Mohanty and R. N. Mahapatra, “IntellBatt: A Smarter Battery Design” IEEE Computer, pp.67-71, March 2010.

[7]  S. K. Mandal, N. Gupta, A. Mandal, J. Malave, J. D. Lee and R. N. Mahapatra, ”NoCBench: A Benchmarking Platform for Network on Chip”, Workshop on Unique Chips and Systems, 2009

[8]  S. K. Mandal, R. N. Mahapatra, “PowerAntz: Distributed Power Sharing Strategy for Network on Chip”, International Symposium on Low Power Electronic Design, 2008

[9]  S. K. Mandal, P. Bhojwani, S. P. Mohanty and R. N. Mahapatra, “IntellBatt: Towards Smarter Battery Design”, Design Automation Conference, 2008.

Work Authorization in US

Authorized to work in the United States through OPT - Available to start from September 2011.